Field effect transistor including an organic semiconductor and a dielectric layer having a substantially same pattern

ABSTRACT

Provided is a method of manufacturing a field effect transistor with an organic semiconductor, and particularly a device comprising a plurality of field effect transistors with an interconnect structure. Herein, use is made of three photolithographical masks for four layers. Thereto, the transistor is provided in a top-gate structure, and the organic semiconductor layer ( 307 ) and the dielectric layer ( 309 ) are structure and patterned together. The semiconductor layer ( 307 ) and the dielectric layer ( 309 ) may be removed from areas not associated with field effect transistors ( 300 ) or with crossing conductors of the first and second conductor layer ( 303, 305, 501 ).

The invention relates to an a method of manufacturing an electronicdevice, in which method at least one field effect transistor comprisingan organic semiconductor layer is provided on a substrate.

The invention also relates to an electronic device comprising aplurality of field effect transistors comprising an organicsemiconductor layer and an interconnect structure so as to connect thetransistors mutually and/or to an output terminal.

It has for many years been known to manufacture electronic semiconductorcomponents such as bipolar and field effect transistors usingsemiconductor materials such as silicon, germanium and gallium arsenide.Specifically, integrated circuits comprising many electronic componentsare manufactured by depositing conductive, semiconductive and dielectriclayers on a substrate.

In recent years, it has been realized that some organic materials, suchas for example pentacene, may exhibit semiconductor properties.Semiconductor components, arrangements and circuits comprising organicsemiconductors promise a number of advantages over traditionalsemiconductor based structures including mechanical flexibility,solution processability, and low temperature processing. Accordingly,much research has been undertaken in the field of organic semiconductorsand the manufacturing of semiconductor components and circuits based onorganic semiconductors.

Currently, organic semiconductor transistors are made by standardphotolithographic methods. FIG. 1 illustrates the structure 100 of anorganic semiconductor in accordance with the prior art. Themanufacturing of the semiconductor comprises a minimum of three or fourmask steps. The semiconductor structure 100 is produced on a substrate101. First the gate layer 103 (usually a metal layer, for example gold)is deposited on the substrate 101 and patterned by photolithography.Then a dielectric layer 105 is deposited (an organic HPR504 layer forexample) and patterned in order to make holes for verticalinterconnects. The third layer 107, 109 is a source-drain layer (forexample made of gold) which is patterned to form the source 107 and thedrain 109 of the transistor. Finally an organic semiconductor 111 isdeposited. The gate-source and gate-drain overlap is usually 5 μm, whichis the same size as is commonly used for the channel length (i.e. thegap between the source and the drain).

Structuring of the semiconductor is desired in order to access theelectrodes of the gate layer. Furthermore, structuring of thesemiconductor layer is preferred in order to reduce leakage current andto avoid the generation of spurious transistors formed by interconnectsof the gate layer 103 crossing semiconductor areas between electrodes ofthe source-drain layer 107, 109. However, the structuring of thesemiconductor requires an additional structuring step thereby making themanufacturing process a four mask process.

Deposition of the various layers is generally a cheap and simpleprocess. For example, spin-coating may be used to cheaply andefficiently distribute a dielectric or semiconductor layer. However,structuring generally uses lithographic techniques which are relativelyexpensive and complicated lithographic techniques. Accordingly, areduction in the manufacturing expense and complexity would beadvantageous.

The conventional method of manufacturing of an organic field effecttransistor comprises processing the source-drain layer betweendeposition of the dielectric and the semiconductor layers. This has atendency of introducing impurities between the dielectric andsemiconductor layer thereby reducing the performance of the transistor.Accordingly, an improved performance and reduced amount of impuritieswould be advantageous.

An electronic device comprising field effect transistors, such as anintegrated circuit, manufactured by the conventional approach typicallyhas one or more layers (e.g. the dielectric layer or the semiconductorlayer) extending over the entire area of the arrangement Thissignificantly reduces the mechanical reliability of the structurecausing increased mechanical stress and reduced mechanical flexibility.Accordingly, an electronic device with field effect transistors and amanufacturing process achieving improved mechanical characteristics androbustness would be advantageous.

Accordingly, the invention preferably seeks to mitigate, alleviate oreliminate one or more of the above mentioned disadvantages singly or inany combination.

According to a first aspect of the invention, there is provided a methodof manufacturing a field effect transistor arrangement on a substrate;the method comprising the steps of: applying a patterned first conductorlayer on the substrate; applying an organic semiconductor layer on thefirst conductor layer; applying a dielectric layer on the semiconductorlayer; patterning the semiconductor layer and the dielectric layertogether; and applying a patterned second conductor layer on thepatterned dielectric layer.

The application of the patterned conductor layers may either be directlyby application of the conductive material in the desired patterns (e.g.by evaporation through a shadow mask) or may be a two step process ofdepositing the conductive material followed by a step of patterning thelayer. Patterning or structuring of a layer generally includes anysuitable means of providing a desired structure or pattern to the layer.

The invention allows for a field effect transistor arrangement to bemanufactured having both a structured dielectric layer and semiconductorlayer while only using three masks. Specifically, by structuring thelayers such that the semiconductor and dielectric layer may patternedtogether, only a single patterning step is required for patterning theselayers. In particular, only a single photolithographic step is requiredfor patterning the semiconductor and dielectric layer thereby reducingthe number of photolithographic steps required to achieve a patterned orstructured semiconductor and dielectric layer.

Thus, the invention enables a 3-mask process for organic electronicswhile achieving structuring of both dielectric and semiconductor layer.As manufacturing of organic electronics combines cheap depositiontechniques with relatively expensive photo-lithography, reduction of themask count is very important and leads to a significant manufacturingcost reduction.

It is an advantage of the invention that the dielectric layer can bedeposited directly on the semiconductor layer before any patterning isperformed. This allows for a very clean interface between these layersthereby improving the mobility in the semiconductor and thus theperformance of the field effect transistor. Specifically, the dielectricand semiconductor layer may be deposited immediately after each otherand in the same environment. This provides for a significantly improvedintegrity of the dielectric-semiconductor interface with significantlyreduced levels of impurities.

The structuring of the dielectric and semiconductor layer furthermoreallows for an increased mechanical flexibility and reduced mechanicalstress. This allows for an improved reliability. Whereas the knownmethod results in a structure, in which the semiconductor layer andparticularly the dielectric layer are at some areas absent, the methodof the invention results therein that the dielectric layer and thesemiconductor layer are at some areas present.

It is a further advantage of the method of the invention that adielectric material with a relatively high dielectric constant may beused for the dielectric layer. Whereas in the prior art method, thedielectric layer functions as a glamorization layer and hence as theinsulation between different transistors, the dielectric layer asprovided in the method of invention has a function in the transistor andat the crossings of limited area.

In a preferred embodiment of the method of the invention the step ofpatterning the semiconductor layer and the dielectric layer comprisesremoving the organic semiconductor layer and the dielectric layer fromareas not associated with the at least one field effect transistor andfrom areas not associated with crossing conductors of the first andsecond conductor layer.

This significantly reduces the mechanical stress and increases theresilience and/or flexibility of the field effect transistorarrangement. Specifically, the semiconductor and dielectric layer may beremoved for a significant proportion of the total area and themechanical properties of the structure may be predominantly determinedby the mechanical properties of the substrate. Specifically, theinvention may allow for flexible or bendable structures or structureshaving increased resistance to vibrations and mechanical shocks.

It is observed that a vertical interconnect is formed at areas where thefirst and second conductor layer overlap and the semiconductor layer andthe dielectric layer are removed. These vertical interconnects are vitalso as to provide the required connections from and to the individualtransistors. Also, the vertical interconnect allows to interconnect thedrain and the gate electrode of one transistor, so that the transistorcan be used as a diode, i.e. for a rectifying function.

In a further, preferred embodiment the said areas associated with afield effect transistor and/or the said areas associated with crossingconductors include protection zones providing a minimal lateral distancebetween a first conductor in the first conductor layer and a secondconductor in the second conductor layer.

As a result of the method of the invention, the semiconductor layerextends to the side faces of the semiconductor-dielectric islands. Asecond conductor extending beyond the island may therefore get incontact to the semiconductor layer. This may lead to a leakage currentbetween this second conductor and a first conductor underlying thesemiconductor-dielectric islands. The provision of protection zonesenlarges the lateral distance between this first and this secondconductor. As the leakage current depends inversely proportional to thelateral distance, it is considerable reduced by these protection zones.The protection zone will generally have a length in the order of 0.5 to10 micrometers, preferably 1-5 micrometers. The resulting shape of thesemiconductor-dielectric island, as seen normal to the substrate planeis then elongated. In another embodiment, the size of the protectionzones is chosen deliberately, so as to provide a resistance of desiredmagnitude between the first and the second conductor.

In one embodiment, the organic semiconductor layer is a polymericsemiconductor layer. Suitable polymeric semiconductor layers includewithout limitation polyarylamines, polyfluorenes,polythienylene-vinylenes, polyphenylene-vinylenes,polyfuranylene-vinylenes, polythiophenes, particularlypoly-3(alkyl)thiophenes. These semiconductor materials may besubstituted with desired alifatic and aromatic side groups so as toimprove the processing thereof. Furthermore, the polymericsemiconductors may be networks and copolymers. These networks andcopolymers may comprise groups which do not exhibit semiconductingbehavior. Suitable examples are described in the non-prepublishedapplication WO-IB03/01062 (PHNL020257).

Alternatively, the organic semiconductor is an oligomeric compound, suchas an oligothiophene and an oligocene, wherein the number of repeatingunits is generally between 3 and 15. Particularly preferred therewith isthe Oligocene with 5 repeating units, generally known as pentacene. Alsothese molecules may have desired side groups, as known per se, and maybe included in polymeric networks and/or copolymers as described in theabove-mentioned application. Pentacene is particularly preferred in viewof its mobility. Further oligomeric and polymeric organic semiconductorsare known to the sldiled person.

It will be understood that a field effect transistor generally comprisesa source and a drain electrode in the first conductor layer adjacent tothe semiconductor layer, and a gate electrode in the second conductorlayer which is separated from the semiconductor layer through thedielectric layer. Particularly, a perpendicular projection of the gateelectrode onto the semiconductor layer has an overlap with the channelin this semiconductor layer between the source and drain electrode. Thegate may for example be a metal layer, such as gold, or may e.g. be anorganic conductor.

According to another feature of the invention, the step of applying anorganic semiconductor layer on the first conductor layer comprisesapplying an organic semiconductor or a precursor thereof by spincoating. This provides for a particularly simple and low costmanufacturing process. The use of a precursor molecule is a well-knowntechnique in the field. The precursor may be converted in thesemiconductor material after its deposition.

According to another feature of the invention, the step of applying andielectric layer on the first conductor layer comprises applying adielectric material by spin coating. This provides for a particularlysimple and low cost manufacturing process. Specifically, the dielectricand semiconductor layers may both be provided by spin coating in thesame spin coating device thereby allowing for a high integration andhigh purity of the interface between the dielectric layer and thesemiconductor layer. The cost and complexity of the manufacturingprocess may be kept low by only using one mask step for patterning thedielectric and semiconductor layers after these have been applied by thelow cost spin coating operation.

In the case that a precursor is applied for the semiconductor, whichneeds conversion at increased temperature, this conversion may takeplace after provision of the dielectric layer. This is particularlysuitable in the case that the dielectric layer also needs a heattreatment (for instance after irradiating it with actinic readiation).Then, both heat treatments may be combined.

Patterning of a layer after deposition of this layer generally involvesthe provision of a mask followed by etching. It is preferred that thestep of patterning the semiconductor layer and the dielectric layercomprises a photolithographic process. Herein, a layer is patternedusing actinic radiation, so as to effect chemical changes in theirradiated layer. This layer can afterwards be used as an etch mask. Aphotolithographic process is particularly suitable for patterning thedielectric and semiconductor layers together.

It is herein particularly preferred that the dielectric layer functionsas a photoresist layer for the lithographic process. Hence, there is noadditional mask needed in the photolithographic process. The dielectriclayer preferably comprises a material that may also function as aphotoresist. Examples of suitable materials include HPR504 or SC100(Olin Hunt). By using the same layer as both an dielectric layer and aphotoresist layer, the need for an application of an additionalphotoresist layer is avoided and thus the complexity and cost of themanufacturing process may be reduced further. Besides, the dielectriclayer comprises preferably an organic material, so as to have excellentflexibility. If a photoresist is provided on top of this dielectriclayer of organic material, a very selective etchant is needed to removethe photoresist mask afterwards without affecting the dielectric layernegatively.

According to another feature of the invention, the method ofmanufacturing further comprises the step of applying a protective layer.The protective layer is preferably added on top of the second conductorlayer and may preferably comprise materials such as polystyrene, Zeonex,PMMA, Polycarbonate, and PVDF. The protective layer provides additionalprotection of the structure and increased mechanical robustness. For adisplay arrangement, the protective layer is preferably substantiallytransparent. In a preferred embodiment of the invention, the electronicdevice comprises a plurality of field effect transistors. Preferablyalso other components including both semiconductor components, includingmemory units and resistive components are present All of these may beprovided in the four layer stack of first and second conductor layer,dielectric layer and semiconductor layer. However, further layers may bepresent in addition hereto. The manufacturing process thus allowscomplicated arrangements with complex functions to be manufactured by alow complexity and cheap manufacturing process. Specifically, the devicemay be an integrated circuit.

In a further preferred embodiment, the electronic device is or comprisesa display arrangement. A display may thus be manufactured by a simpleand cheap manufacturing process. The field effect arrangement (e.g. thestack of layers in which the field effect transistors are provided) willtypically form only part of the display. The patterning of both thedielectric and semiconductor layer may provide for improved mechanicalproperties including reduced stress and increased flexibility.Specifically, a bendable display may be manufactured.

In an even further embodiment, the substrate is substantiallytransmissive. This allows for a display arrangement wherein a displayedpicture may be viewed through the substrate and the substrate isaccordingly preferably sufficiently transparent for a picture to beviewed through the substrate.

The choice of the electro-optical layer in the display basicallydetermines the operation principle of the display. A well-knownelectro-optical layer is a layer of liquid-crystalline material. It ishowever preferred that an electrophoretic electro-optical layer isprovided. This provides for a particularly suitable, simple and low costmethod of manufacturing a display. Particularly, the rate at which thedisplay has to be refreshed, is lower for electrophoretic displays thanfor liquid crystalline displays, and hence the energy consumption isreduced. The display is in this sense very suitable for use in mobiletelecommunication applications, where power management is an absolutemust. A further feature of the electrophoretic display is that thedisplay quality from viewing angles smaller than 90 degrees, is quitegood. This is important for a bendable display, in which this viewingangle will be more often unequal to 90 degrees with respect to the planeof the display.

According to a second aspect of the invention, there is provided anelectronic device comprising a plurality of field effect transistorscomprising an organic semiconductor layer and an interconnect structureso as to connect the transistors mutually and/or to an output terminal,which field effect transistors are provided in a stack comprising: apatterned first conductor layer applied on the substrate; an organicsemiconductor layer applied on the first conductor layer, an dielectriclayer applied on the semiconductor layer; a patterned second conductorlayer applied on the dielectric layer. According to the invention, thesemiconductor layer and the dielectric layer are patterned according toa substantially identical pattern. As a consequence, the interface ofthe semiconductor and the dielectric layer is very pure, and therewithprovides an improved transistor performance, particularly an improvedcarrier mobility.

In the device of the invention the semiconductor and the dielectriclayer are preferably removed from areas from areas not associated withthe at least one field effect transistor and from areas not associatedwith crossing conductors of the first and second conductor layer. Thisleads thereto, that the device has an improved mechanical performancedue to the patterning of both the dielectric and semiconductor layer.

These and other aspects, features and advantages of the invention willbe apparent from and elucidated with reference to the embodiment(s)described hereinafter.

An embodiment of the invention will be described, by way of exampleonly, with reference to the drawings, in which

FIG. 1 illustrates the structure of an organic semiconductor inaccordance with the prior art;

FIG. 2 illustrates a flow chart of a method of manufacturing a fieldeffect transistor arrangement in accordance with an embodiment of theinvention;

FIG. 3 shows a cross section of a field effect transistor structurefollowing application of an dielectric and semiconductor layer inaccordance with an embodiment of the invention;

FIG. 4 shows a cross section of the field effect transistor structurefollowing patterning of the dielectric and semiconductor layer inaccordance with an embodiment of the invention;

FIG. 5 shows a cross section of the field effect transistor structurefollowing deposition of the second conductor layer in accordance with anembodiment of the invention;

FIG. 6 shows a top-view of a crossing of two conductors of the differentconductor layers;

FIG. 7 shows a cross-section view corresponding to the top view of FIG.6;

FIG. 8 shows a top-view of a second embodiment of a crossing of twoconductors of the different conductor layers; and

FIG. 9 shows a cross-section view corresponding to the top view of FIG.8.

FIG. 2 illustrates a flow chart of a method of manufacturing an organicfield effect transistor (FET) arrangement in accordance with a preferredembodiment of the invention. The organic field effect transistor isprovided on a substrate, which was glass in the experiment used fortesting. Usually, this substrate is attached to a carrier which providesthe support and mechanical stability for the FET structure. Then, thecarrier is made of glass and the substrate is in this case a polymericfoil, for instance made of polyimide. The substrate may be removed fromthe carrier in suitable manner. Preferred is a method wherein thesubstrate is attached to the carrier with an UV-releasable adhesive.Detachment occurs then on irradiation of the UV-releasable adhesivethrough the—transparent—carrier.

In step 201 of the manufacturing process a structured or patterned firstconductor layer is applied to the substrate. In the preferredembodiment, a gold layer is applied to the substrate followed by asubsequent lithographic patterning of the gold layer as is well known inthe art

In the preferred embodiment, the sources and drains of FETs are formedby the first conductor layer, and the patterning of the first conductorlayer is such as to provide source and drain electrodes at theappropriate locations. In addition, the first conductor layer provides afirst interconnect layer for forming the interconnects required forimplementing an electronic circuit.

In step 203, an organic semiconductor layer is applied on the firstconductor layer. In the preferred embodiment, the semiconductor layer isthus applied on top of the first conductor layer. The applied layercovers the substrate area and is thus in contact with the firstconductor layer and directly with the substrate where the firstconductor has been removed by the patterning.

In the preferred embodiment, the organic semiconductor layer ispentacene (0.25 weight %, with 10% polystyrene added to the solution),which is preferably applied to the substrate as a precursor. Theprecursor used is6,13-dihydro-6,13-(2,3,4,5-tetrachloro-2,4-cyclohexadieno)-pentacene. Itis applied on first conductor layer by spin coating. Following spincoating, conversion of the precursor into pentacene is performed for 10seconds at 200° C. on a hot plate.

In step 205 of the manufacturing process, a dielectric layer is appliedon top of the semiconductor layer. The dielectric layer is preferablyapplied by spin coating and preferably in the same operation as theapplication of the semiconductor layer in step 203. The dielectric layeris in the preferred embodiment a dielectricum having suitablecharacteristics and may preferably be a photoresist (such as HPR504).

In the case that a precursor of the semiconductor is applied, theconversion into the actual semiconductor may take place after thedielectric layer has been applied. In case that the dielectric layer,particularly a photoresist, needs curing after application (andphotolithographic treatment), the conversion of the precursor into thesemiconductor and the curing of the dielectric layer may be combined ina single treatment. This heating treatment may comprise heating atseveral temperatures for different periods.

Following the application by spin coating, the dielectric layer is, inthe preferred embodiment, dried on a hot plate for 30 sec. at 90° C.

FIG. 3 shows a cross section of a FET structure 300 followingapplication of the dielectric and semiconductor layer in accordance withan embodiment of the invention. Hence, FIG. 3 illustrates a crosssection of the FET structure following step 205.

As illustrated in FIG. 3, a source 303 and a drain 305 is formed by thefirst conductor layer 303, 305 formed on top of the substrate 301. Thesemiconductor layer 307 is deposited on top of the first conductor layer303, 305 and is in contact with this and the substrate 301. On top ofthe semiconductor layer, the dielectric layer 309 is deposited.

In step 207, the semiconductor layer and the dielectric layer arepatterned or structured together. Specifically, both the semiconductorand the dielectric layer are patterned in a single operation or step.Thus, the same mask is applied to both layers and the two layers willend up having substantially the same pattern.

In the preferred embodiment, the patterning of the semiconductor anddielectric layers is by a photolithographic process. In the preferredembodiment, the dielectric layer is chosen such that the dielectriclayer may also function as a photoresist layer. For example, HPR504 maybe used for the dielectric layer. In this embodiment, the structure isexposed to UV-light via a contact mask and then developed and rinsed.The patterning of the dielectric and semiconductor layers is thenachieved by a conventional etching process such as by Reactive IonEtching (RIE) with fi. Ar/O₂ gas.

Thus, patterning or structuring of the semiconductor-dielectric stack isextremely simple for the described device, as the used dielectricmaterial is photosensitive, and therefore acts as the resist for etchingthe semiconductor. This obviates the requirement of an additionalphotoresist layer on top of the stack.

If the substrate is a polymer foil, such as polyimide, the etching mayextend into the substrate. There are several ways to limit the negativeimpact thereof. First of all, the etching times and conditions can beoptimized. The properties and thicknesses of the semiconductor layer andthe dielectric layer are well-known, and thus is optimalizationpossible. Secondly, an etch stop layer can be provided on the substrateor be part of the substrate. Etch stop layers are known per se.Preferably use is made of an electrically insulating material, therewithpreventing any capacitive coupling or short-circuitry between the secondconductor layer and the etch stop layer.

Particularly suitable materials for etch stop layers are polymers filledwith particles, particularly nanoparticles. Suitable polymers includepolyimide, polystyrene, polyimide, polyethyleneterephtalate and so on.Suitable nanoparticles include carbon black, SiO₂, TiO₂, BaTiO₃,ferrites, as well as other inorganic compounds and particularly oxides.The nanoparticles may have a diameter in the order of 1 nm up to 500 nm.Such polymers filled with nanoparticles have the following advantageousproperties: they can be used as etch stop, the surface of the layer isrelatively flat, therewith allowing direct deposition of the secondconductor layer, the layer is flexible, and the polymer can be chosen sothat the resulting layer has a thermal coefficient of expansion that iscomparable to the substrate and to the other layers. It is a furtheradvantage, that with a suitable choice of the particles, the resultingetch stop layer may inhibit radiation as well, so as to protect theorganic semiconductor layer against radiation that leads to degradation.

In the preferred embodiment, the organic semiconductor layer and thedielectric layer is removed from areas not associated with components ofthe field effect transistor arrangement or with crossing conductors ofthe first and second conductor layer.

In contrast to conventional methods, the patterning of the semiconductorlayer is in the preferred embodiment combined with the process of makingthe vias and interconnects in the dielectric layer. This reduces thenumber of masks required by the process from four to three which resultsin a significant cost reduction of the manufacturing process.Preferably, the dielectric layer is removed everywhere except for thetransistor area and the area of the crossings between the two conductinglayers. An additional advantage is that it increases the mechanicalflexibility of the device, as removal of the dielectric layer reducesthe stress and consequently the chance of cracks and film peeling.

FIG. 4 shows a cross section of the FET structure 300 followingpatterning of the dielectric and semiconductor layer in accordance withan embodiment of the invention. Hence, FIG. 4 illustrates a crosssection of the FET structure following step 207. As can be seen in FIG.4, the semiconductor and dielectric layers 307, 309 have been reduced tothe area above the source and drain electrodes.

In step 209, a patterned second conductor layer is deposited on thepatterned dielectric layer. In the preferred embodiment, the secondconductor layer accommodates a gate of the field effect transistor. Inthe preferred embodiment, a patterned gold gate layer is directlyapplied by evaporation through a shadow mask. However, in otherembodiments, a two stage process of application of a conductive layerfollowed by patterning may be used. In some embodiments an organicconductor material may be used for the gate.

FIG. 5 shows a cross section of the FET structure 300 followingdeposition of the second conductor layer in accordance with anembodiment of the invention. Hence, FIG. 5 illustrates a cross sectionof the FET structure following step 209.

As can be seen in FIG. 5, a gate electrode 501 has been provided on topof the dielectric layer. Thus a FET has been formed having a channelbetween a source 303 and drain 305 electrode and an overlaying gate 501.Thus, a very simple manufacturing process using only three masks whilestructuring both the semiconductor and dielectric layer is achieved fora top gate structure organic FET.

FETs may be produced having a very clean integration of thesemiconductor and dielectric layer whereby high performance of theorganic FET can be achieved. Experiments have shown that a mobility of2.10⁻² cm²/Vs can be achieved. This is comparable to or better than theconventional bottom gate structures under the same conditions.

In the preferred embodiment, the insulation layer is removed from allareas not associated with components of the field effect transistorarrangement or with crossing conductors of the first and secondconductor layer. Hence, the dielectric layer and thus the semiconductorlayer is maintained when interconnects of the two layers cross in orderto provide the required isolation between these.

FIG. 6 shows a top-view of a crossing of two conductors of the differentconductor layers. A first conductor 601 of the first lower conductorlayer crosses substantially perpendicularly under a second conductor 603of the upper second conductor layer. The two conductors 601, 603 areisolated by an area or island 605 of dielectric material of thedielectric layer.

FIG. 7 shows a cross-section of the crossing of the two conductors 601,603 of the different conductor layers. As shown in FIG. 7, the island605 of dielectric material causes an island 701 of semiconductormaterial to remain. However, this semiconductor island is in contactwith both conductors 601, 603 and accordingly a leakage path is formedbetween the two conducting layers. This leakage path can be made assmall as required by choosing the right geometry of thedielectric-semiconductor island 605, 701. An extreme case, where theleakage is completely removed, could be the extension of the islandcompletely under the top conducting electrode 603.

FIG. 8 shows schematically a top view of a second embodiment of thecrossing of two conductors 601,603 of the different conductor layers.FIG. 9 shows the corresponding cross-sectional view. The referencenumbers used herein are identical to those in FIG. 6 and 7, as far aspossible. In this embodiment the island 605 of dielectric andsemiconductor layers is elongated with respect to the island shown inFIG. 6. This is done in order to provide protection zones 702. Theseprotection zones 702 provide a minimal lateral distance between thefirst conductor 601 in the first conductor layer and the secondconductor 603 in the second conductor layer. The protection zone is inthis example about the 5.0 micrometer. The width of the second conductoris about 2.0 micrometer. Pentacene has a conductivity of 1,3.10⁻⁴ S/cm.This results in a resistance of about 2.10⁴ Ω. As the voltagedifferences between the first conductor 601 and the second conductor 603will only be of substantial magnitude at short periods, this is notproblematic.

Thus, in accordance with the preferred embodiment, a single organic FETmay be produced by the described manufacturing process or an organic FETarrangement comprising a plurality or multitude of FETs may bemanufactured. In some embodiments, an integrated circuit is manufacturedcomprising both semiconductor components as well as interconnectsrequired to achieve a desired functionality.

In some embodiments, the FET arrangement may used in a display orelectroluminescent device. Specifically, pixel FETs may be produced inaccordance with the described method. In this case, the FET arrangementpreferably comprises a number of FETs arranged in a matrix formatcomprising rows and columns. The gate of each pixel FET is preferablyconnected to a row electrode and the source of each FET is preferablyconnected to a column electrode. Each individual pixel FET may then beactivated and provided with the appropriate charge by a scanningoperation as is well known to the person skilled in the art.

For some display application, at least one of the substrate istransmissive and preferably sufficiently transparent for an image to beseen through the layer. This allows for the image to be seen from thecorresponding direction by light penetrating the appropriate layer.

In the preferred embodiment for a display application, the manufacturingprocess further comprises the step of applying an electrophoreticelectro-optical layer. The electrophoretic electro-optical layer willcomprise charged particles, which will move dependent on the chargeapplied to the pixel transistor thereby creating a visual coloration ofthe pixel in accordance with the applied charge.

In the preferred embodiment, the manufacturing further comprises thestep of applying a protective layer. For example, a protective layer ofpolymethylmethacrylate, polyvinylalcohol, polyvinylphenol, polyacrylate,polystyrene, polyvinylchloride, polyesters, polyethers,benzocyclobutene, polyinide, epoxides, glassfilled polymers or inorganicdielectrics may be applied by spin coating following the application ofthe second conductive layer or the electrophoretic layer. This,protective layer will increase the mechanical resistance of the device.

The invention can be implemented by any suitable apparatus and in anysuitable form. The elements and components for implementing anembodiment of the invention may be physically, functionally andlogically implemented in any suitable way. Indeed the functionality maybe implemented in a single unit, in a plurality of units or as part ofother units. As such, the invention may be implemented in a single unitor may be physically and functionally distributed between differentunits.

Although the present invention has been described in correction with thepreferred embodiment, it is not intended to be limited to the specificform set forth herein. Rather, the scope of the present invention islimited only by the accompanying claims. In the claims, the termcomprising does not exclude the presence of other elements or steps.

Furthermore, although individually listed, a plurality of means,elements or method steps may be implemented by e.g. a single unit.Additionally, although individual features may be included in differentclaims, these may possibly be advantageously combined, and the inclusionin different claims does not imply that a combination of features is nofeasible and/or advantageous. In addition, singular references do notexclude a plurality. Thus references to “a”, “an”, “first”, “second” etcdo not preclude a plurality.

1. A method of manufacturing an electronic device, in which method atleast one field effect transistor is provided on a substrate, whichprovision of the at least one field effect transistor comprises thesteps of: applying a patterned, first conductor layer on the substrate;applying an organic semiconductor layer on the first conductor layer;applying a dielectric layer on the semiconductor layer; patterning theorganic semiconductor layer and the dielectric layer together; andapplying a patterned second conductor layer on the patterned dielectriclayer.
 2. A method as claimed in claim 1 wherein the step of patterningthe organic semiconductor layer and the dielectric layer comprisesremoving the organic semiconductor layer and the dielectric layer fromareas not associated with the at least one field effect transistor andfrom areas not associated with crossing conductors of the first andsecond conductor layer.
 3. A method as claimed in claim 1 wherein thestep of applying an organic semiconductor layer on the first conductorlayer comprises applying an organic semiconductor or a precursor thereofby spin coating.
 4. A method as claimed in claim 1 wherein thedielectric layer comprises an initiator sensitive for actinic radiationand functions after irradiation as a mask for the patterning of thesemiconductor layer.
 5. A method as claimed in claim 1, comprising theadditional step of providing an electro-optical layer so as to provide adisplay arrangement.
 6. A method as claimed in claim 2, wherein the saidareas associated with a field effect transistor and/or the said areasassociated with crossing conductors include protection zones providing aminimal lateral distance between a first conductor in the firstconductor layer and a second conductor in the second conductor layer. 7.A method as claimed in claim 3, wherein the dielectric layer comprises aphotoresist material.
 8. A method as claimed in claim 7 wherein thesubstrate is substantially transparent.
 9. An electronic devicecomprising a plurality of field effect transistor on a substrate and aninterconnect structure so as to connect the transistors mutually and/orto an output terminal, the fleid effect transistors and at least part ofthe interconnect structure being provided in a stack of: a patternedfirst conductor layer applied on the substrate; an organic semiconductorlayer applied on the first conductor layer; a dielectric layer appliedon the semiconductor layer; a patterned second conductor layer appliedon the dielectric layer; wherein the semiconductor layer and thedielectric layer are provided in a substantially identical pattern. 10.An electronic device as claimed in claim 9, wherein the semiconductorlayer and the dielectric layer are absent from areas not associated withthe field effect transistors and from areas not associated with crossingconductors of the first and second conductor layer.